FPGA based Design and Simulation of Extended Golay Codec with Hardware Optimization for high speed Applications

Abstract

In wireless communication systems the ability of the receiver to detect and correct the error from the received information is become one of the most important issue, so as to provide the processor the correct information data. To achieve this there are numbers of such methods are available to implement the hardware and software. But, length of the communication link plays an important role because the distance of the transmitter and the receiver depends on the length as length increases the distance between the transmitter and the receiver, and multiple bits of the transmitted information may change due to the effect of noise on the transmitted signal. This can cause extreme loss in many cases. This paper presents a brief of Field Programmable Gate Array (FPGA) based design and simulation of Golay Code (G23) and Extended Golay Code (G24) Encoding scheme. This paper using the Golay Encoder to work on the optimization of the time delay of the operational circuit to encode a data packet.