Area Efficient, Low Power 4:1 Multiplexer using NMOS 45nm Technology

Abstract

The field of electronics is trending with miniaturization and reduction in the threshold voltage. In this paper, we dealt with the efficient use of die area and optimum usage of power. This paper shows the contrast between “conventional MUX” and “MUX using NMOS transistors” and accentuates the advantages of the latter. The conventional 4:1 MUX consisted of a total of four AND gates and few inverters which made it occupy more die area but in this paper we have presented the design of 4:1 MUX which occupies less area on the die. Multiplexer is a device which works on the principle of MISO (Multiple Input Single Output).