Design of Reconfigurable Network-on-Chip Topology

Abstract

A Network-on-Chip (NoC) is used instead of buses to provide better interconnection between the IP modules, as the number of IPs in a SoC increases. The use of NoC enables the SoC designer to find suitable solution for different characteristics and constraints. The reconfigurable Network-on-Chip architecture aims at gaining low latency and low power consumption. As different applications have different requirements and the NoC should be flexible enough to meet these requirements. In this NoC architecture design we aim to combine both packet switching and circuit switching. By combining these two switching techniques it becomes possible to generate application specific topologies on a general Network-on-Chip based system.