Design of Vedic ALU for 16-Bit Processor

Abstract

The main objective of this project is to design a VEDIC ALU for a 16-bit processor. The Arithmetic operations in the ALU are performed using the few of the 16 sutras of Vedic Mathematics. Even though, addition and subtraction sutras are similar to the conventional methods, multiplication and division methods are derived and implemented successfully in ALU using the Vedic sutras. The advantage of implementing Vedic sutras for Multiplication and Division is the faster speed and reduced hardware. It also reduces the total power consumption as compared to the conventional ALU which is currently being used. The platform for designing the Vedic ALU is XILINX ISE and the preferred language is Verilog. Vedic Mathematics is the Ancient Indian technique of Mathematics, derived from ancient Vedas, that was rediscovered in 20th century by Swami Sri Bharati Krishna Tirthaji Maharaj.