Implementation of Low Power Multiplexer usign Adiabatic Logic

Abstract

Adiabatic logic is a low power logic based on charge recovery principle. In this paper, an adiabatic logic based 2x1 multiplexer and 4x1 multiplexer are designed on the basis of Two-Phase Adiabatic Static Clocked Logic (2PASCL) technique. The power dissipation of proposed technique is compared with conventional CMOS technique according to the various values of input signal switching frequencies, number of active devices and total nodes. The simulation is performed on S-edit of TANNER tools with BSIM4 at 90nm technology.