An Efficient Implementation of Wallace Tree Multiplier

Abstract

In Very large Scale Integration (VLSI) technology, power consumption and speed are the two important constraints for determining the efficiency of the architecture. This paper aspires at declining this parameters of the Wallace tree multiplier with the efficient use of modified Booth encoding and compressors.The proposed architecture is employed in Verilog HDL and it is simulated in Cadence NC Sim and synthesized using Encounter RTL Compiler in 180nm Taiwan Semiconductor Manufacturing Company(TSMC) slow library .The proposed architecture is found to be 42.2% faster than the conventional Wallace tree architecture and the power consumption lowered by 45% as compared to the conventional Wallace Tree.