Design And Analysis of 1-Bit Full Adder and Logic Gates

Main Article Content

M. K. Musale, Prof. S. M. Turkane


The scaling of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) are commonly used in high speed integrated circuits, yield smaller and faster more functions at lower cost. Various problems exist with scaling of MOSFET devices i.e. short channel effects (SCE), drain induced barrier lowering, velocity saturation which limits the performance of MOSFETs. Scaling limitations of MOSFET devices leads to lower ON to OFF current ratio limited by 60mV/dec sub threshold slope.A new type of device called “Tunnel FET” is used to overcome these difficulties. TFET can beat 60mV/dec sub-threshold swing of MOSFETs. In Tunnel FET the carrier are generated by band-to-band tunneling and OFF current is low. Tunnel FET have energy barrier in OFF state, which avoids application where leakage is concern of interest. In this Project sub-threshold swing and low OFF current is simulated and its power is analyzed.Basically in VLSI circuit like design of IC we have to simulate all the parameters of the devices & circuit regarding of that IC or any devices like FET, MOSFET, CMOS etc. In device simulation we are most widely use software named as “HSPICE”. We are doing analysis of full bit adder. We are going to compare different characteristics.

Article Details

How to Cite
, M. K. M. P. S. M. T. “Design And Analysis of 1-Bit Full Adder and Logic Gates”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 6, no. 2, Feb. 2018, pp. 73-77, doi:10.17762/ijritcc.v6i2.1424.