Low Power Dissipation in Johnson Counter using DFAL Technique

Abstract

This paper presents a new method for minimizing power dissipation in 4-bit Johnson counter in which Diode-Free adiabatic Logic(DFAL) is used.Power dissipation of the diodes is eliminated by removing diodes from charging and discharging path.Performance of the proposed logic is analyzed and compared with that of CMOS based circuits. All the simulation are carried out in VIRTUOSO spectre simulator of CADENCE 90nm technology .The paper provides low power dissipation using DFAL logic,which has shown better improvement than conventional CMOS design.