Layout and Analysis of different Current Mirror using 45nm Technology

Abstract

This paper proposes new current mirror layout strategies of the circuits which are designed by 45nm technology in Pspice using Tanner Eda tool. Layout strategies help to reduce the matching sensitivity to the linear parameter gradients. The performance of circuit is also analyzed with the help of waveforms generated in W-edit window by varying the input voltage and current values or by changing the arrangement of Mosfet. Simulation results show a significant improvement in matching characteristics of the proposed structures over what is achievable with existing layout techniques in demanding applications.[21]