Design of suitable Magnitude Comparator Architecture for Big Data Analytics

Abstract

In today’s digital era increasing use of portable devices forces electronic designer to concentrate on high speed and low power dissipation. As magnitude comparator is very basic arithmetic unit, to cope up with high speed and optimum power for big data, we need suitable magnitude comparator architecture, so this Paper presents different types of magnitude comparator architecture such as serial, parallel and tree structure. Proposed 64 bit magnitude comparator is designed with 1.8v voltage supply using in standard CMOS 180nm Technology using Cadence Virtuoso EDA tool. Simulation of all three architecture have been done using SPECTRE VIRTUOSO ADE tool.