“Design and Implementation of Low power, High Performance FINFET –Based SRAM Cells”.

Abstract

This research paper presents a comprehensive analysis ofelectrical simulations of FinFET-based SRAMs conducted across various technological nodes to conduct a comprehensive examination of static and energy liability behavior.. The second step, we are designing 14nm, 12 nm and 7 nm  FinFETs and extracting their characteristics by using Sentaurus TCAD. Simulated results of the device shows that it can be governed at the nanometer - scale regime and itsperformance  is analyzed in terms of power consumption, propagation delay, power delayproduct (PDP)  for nanoscaledtechnologies.Furthermore a digital register-transfer level (RTL) structure focusing on the implementation of static random access memory (SRAM) was studied meticulously to evaluate read and write operations controlled by configurable bit lines with multi-level voltage applications. CMOS circuits are implemented using the MICROWIND tool, facilitating accurate representation and simulation of SRAM components. The analysis includes an assessment of voltage-versus-current characteristics and an evaluation of the structural parameters of Double Gate (DG) FinFET transistors within the RTL structure. The 6T SRAM cell architecture is explored, highlighting its importance in the memory hierarchy and emphasising stability and performance considerations. The study also scrutinises system performance concerning input frequency through delay lines, providing insights into responsiveness and speed. Simulation analyses across different CMOS technologies and frequencies offer a thorough understanding of SRAM behaviour, aiding in optimisation and refinement for practical applications.