RISC-V Processor for IOT Applications

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Rajveer Singh, Manu Bansal, Anil Singh


RISC-V is a recently introduced instruction-set architecture (ISA) that offers innovative advantages, including low power consumption, affordability, and scalability. Utilizing an open, non-proprietary Instruction Set Architecture (ISA) enables the creation of on-the-fly design of soft error countermeasures at the microarchitecture level. This may significantly enhance the resilience of Application Specific Standard Products (ASSP) and FPGA implementations. This paper offers a quick overview of the RISC-V architecture. This paper presents a plan to create and execute a 32-bit single-cycle RISC-V processor using Verilog HDL in the Vivado software.

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How to Cite
Rajveer Singh, et al. (2023). RISC-V Processor for IOT Applications. International Journal on Recent and Innovation Trends in Computing and Communication, 11(11), 701–705. https://doi.org/10.17762/ijritcc.v11i11.10074