, Korra Ravi Kumar, Santhosh Kumar Allenki, G.Ramesh. “FPGA Implementation of Area, Delay and Power Efficient Carry Select Adder Architecture Design”. International Journal on Recent and Innovation Trends in Computing and Communication 3, no. 5 (May 31, 2015): 2537–2540. Accessed March 29, 2024. https://ijritcc.org/index.php/ijritcc/article/view/4280.