, L.Malathi, Dr.A.Bharahi, Dr. A.N.Jayanthi, S.Munaf. 2017. “Design of Fast Integer Pipelined Multipliers for CMOS 64-Bit Synchronous and AsynchronousLogic With Adaptable Latency”. International Journal on Recent and Innovation Trends in Computing and Communication 5 (1):99-102. https://doi.org/10.17762/ijritcc.v5i1.96.