, Shyamali Padhi, Swati Verma, Anita Angeline.A, V S Kanchana Bhaaskaran. 2016. “Leakage Reduction Techniques In CMOS Dynamic Logic Circuits”. International Journal on Recent and Innovation Trends in Computing and Communication 4 (3):483-87. https://doi.org/10.17762/ijritcc.v4i3.1923.