, K. R. K. S. K. A. G. FPGA Implementation of Area, Delay and Power Efficient Carry Select Adder Architecture Design. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 3, n. 5, p. 2537–2540, 2015. DOI: 10.17762/ijritcc.v3i5.4280. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/4280. Acesso em: 26 apr. 2024.