, E. R. K. E. A. S. B. Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unit. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 5, n. 7, p. 835 –, 2017. DOI: 10.17762/ijritcc.v5i7.1146. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/1146. Acesso em: 18 may. 2024.