, L. D. D. A. S. Design of Fast Integer Pipelined Multipliers for CMOS 64-bit Synchronous and AsynchronousLogic with Adaptable Latency. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 5, n. 1, p. 99–102, 2017. DOI: 10.17762/ijritcc.v5i1.96. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/96. Acesso em: 27 jul. 2024.