, S. D. P. R. G. J. Implementation of Low Power and Area Efficient 2-Bit/Step Asynchronous SAR ADC using Successively Activated Comparators. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 3, n. 12, p. 6577–6581, 2015. DOI: 10.17762/ijritcc.v3i12.5098. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/5098. Acesso em: 27 jul. 2024.