, S. D. K. R. P. Architecture and Design of Generic IEEE-754 Based Floating Point Adder, Subtractor and Multiplier. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 3, n. 5, p. 2690–2694, 2015. DOI: 10.17762/ijritcc.v3i5.4310. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/4310. Acesso em: 27 jul. 2024.