, S. M. M. Analysis of Digitally Controlled Delay Loop-Nand Gate For Glitch Free Design. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 3, n. 2, p. 529–533, 2015. DOI: 10.17762/ijritcc.v3i2.3854. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/3854. Acesso em: 27 jul. 2024.