, S. R. M. P. P. S. S. Design and Implementation of Wishbone Bus Interface Architecture for SoC Integration USING VHDL ON FPGA. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 2, n. 7, p. 1847–1850, 2014. DOI: 10.17762/ijritcc.v2i7.3413. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/3413. Acesso em: 28 jul. 2024.