, M. S. S. P. P. M. Design of Wallace Tree Multiplier with Power Efficient Adiabatic Logic. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 2, n. 9, p. 2923–2926, 2014. DOI: 10.17762/ijritcc.v2i9.3322. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/3322. Acesso em: 27 jul. 2024.