, I. S. T. K. Partial Address Field Architectures For Energy Efficient Caches in Embedded Systems - A Review. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 2, n. 9, p. 2814–2818, 2014. DOI: 10.17762/ijritcc.v2i9.3302. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/3302. Acesso em: 27 jul. 2024.