, K. S. W. Power Optimization of I/O Ports Using Clock Gating TechniqueÂ. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 2, n. 6, p. 1761–1763, 2014. DOI: 10.17762/ijritcc.v2i6.3251. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/3251. Acesso em: 12 sep. 2025.