, J. K. P. S. Validation of Octanary Adders in VHDL. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 4, n. 6, p. 71–74, 2016. DOI: 10.17762/ijritcc.v4i6.2256. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/2256. Acesso em: 18 jul. 2024.