, U. R. P. R. T. FPGA based Design and Simulation of Extended Golay Codec with Hardware Optimization for high speed Applications. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 4, n. 5, p. 30–35, 2016. DOI: 10.17762/ijritcc.v4i5.2115. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/2115. Acesso em: 27 jul. 2024.