, S. P. S. V. A. A. V. S. K. B. Leakage Reduction Techniques In CMOS Dynamic Logic Circuits. International Journal on Recent and Innovation Trends in Computing and Communication, [S. l.], v. 4, n. 3, p. 483–487, 2016. DOI: 10.17762/ijritcc.v4i3.1923. Disponível em: https://ijritcc.org/index.php/ijritcc/article/view/1923. Acesso em: 27 jul. 2024.